Saludos
--contador up-down bcd
--con entradas de reset(clr) y enable
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity counter is
port(
clk: in std_logic;
clr: in std_logic;
en: in std_logic;
q: out std_logic_vector(3 downto 0)
);
end counter;
architecture behavioral of counter is
signal qtemp: std_logic_vector(3 downto 0):="0000";
signal ctrl: std_logic := '0';
begin
process(clk, clr)
begin
if clr='0' then
qtemp<=(others=>'0');
elsif rising_edge(clk) then
if en='1' then
if ctrl = '0' then --up
qtemp<=qtemp+1;
if qtemp=8 then
ctrl<='1';
end if;
else
qtemp<=qtemp-1;
if qtemp=1 then
ctrl<='0';
end if;
end if;
end if;
end if;
end process;
q<=qtemp;
end behavioral;
