LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY piso_register IS
GENERIC( x: INTEGER:=8);
PORT( Data_IN: IN std_logic_vector((x-1) DOWNTO 0); --8 Bits
Clock, Reset, Direction, SH_nLD: IN std_logic;
Q: OUT std_logic);
END piso_register;
ARCHITECTURE description OF piso_register IS
SIGNAL Q_Temp: std_logic_vector((x-1) DOWNTO 0):=(OTHERS=>'X'); --Inside Q
BEGIN
SHIFT_PROCESS: PROCESS(Clock, Reset)
BEGIN
IF (Reset='1') THEN
Q_Temp<=(OTHERS=>'0');
ELSIF RISING_EDGE(Clock) THEN
IF(SH_nLD='0') THEN
--CARGA DE DATOS
Q_Temp<=Data_IN;
ELSIF (SH_nLD='1' AND Direction='1') THEN
--DESPLAMIENTO DERECHA
Q_Temp((x-2) DOWNTO 0)<=Q_Temp((x-1) DOWNTO 1);
Q_Temp(x-1)<='0';
ELSIF (SH_nLD='1' AND Direction='0') THEN
--DESPLAZAMIENTO IZQUIERDA
Q_Temp((x-1) DOWNTO 1)<=Q_Temp((x-2) DOWNTO 0);
Q_Temp(0)<='0';
END IF;
END IF;
END PROCESS SHIFT_PROCESS;
WITH Direction SELECT
Q<= Q_Temp(0) WHEN '1',
Q_Temp(x-1) WHEN '0',
'X' WHEN OTHERS;
END description;
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