LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY siso_register IS
GENERIC(x: integer:=8);
PORT( Data_IN: std_logic;
Q: OUT std_logic;
Direction, Clock, Reset, SH: IN std_logic);
END siso_register;
ARCHITECTURE description OF siso_register IS
SIGNAL Q_Temp: std_logic_vector((x-1) DOWNTO 0):=(OTHERS=>'X');
BEGIN
SHIFT_PROCESS: PROCESS(Clock, Reset)
BEGIN
IF (Reset='1') THEN
Q_Temp<=(OTHERS=>'0');
ELSIF RISING_EDGE(Clock) THEN
IF(SH='1' AND Direction='1') THEN
--Desplazamiento Derecha
Q_Temp((x-2) DOWNTO 0)<=Q_Temp((x-1) DOWNTO 1);
Q_Temp(x-1)<=Data_IN;
ELSIF (SH='1' AND Direction='0') THEN
Q_Temp((x-1) DOWNTO 1)<=Q_Temp((x-2) DOWNTO 0);
Q_Temp(0)<=Data_IN;
--Desplazamiento Izquierda
END IF;
END IF;
END PROCESS SHIFT_PROCESS;
WITH Direction SELECT
Q <= Q_Temp(0) WHEN '1',
Q_Temp(x-1) WHEN '0',
'X' when OTHERS;
END description;
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